First Generation Technology (CF1™)

Basic CF1™ Structure

Patent_Drawing

U. S. Patent 5,841,193 (application filed May 20, 1996; patent issued Nov. 24, 1998)

Value Proposition

 

• EPIC CF1™ PROVIDES THE SMALLEST SIZE, HIGHEST PERFORMANCE, AND LOWEST COST SOLUTION FOR SEMICONDUCTOR PACKAGING PROBLEMS THAT REQUIRE I/O OUTSIDE THE CHIP AREA

• ALTERNATIVE TECHNOLOGIES (E.G. BGA) PROVIDE SEPARATE SUBSTRATE WIRING AND CHIP INTERCONNECT (I.E. WIREBOND OR FLIP CHIP).  EPIC CF1™ PROVIDES THESE FUNCTIONS IN A SINGLE, LOW COST, INTEGRATED STRUCTURE.
Basic CF1™ Process
CF!_Process
Technology Drivers

• THE ECONOMIC EFFICIENCIES OF WAFER-LEVEL PACKAGING WITH REDISTRIBUTION BEYOND THE CHIP AREA

• THE HIGH COST OF FINE PITCH WIRE BONDING

• THE DESIRE FOR THE THINNEST PACKAGE WITH THE SMALLEST FOOTPRINT

• THE NEED FOR UNSURPASSED THERMAL AND ELECTRICAL PERFORMANCE

Second Generation Technology "CF2™"

CF2™ Stacked Package Structure

Patent_Drawing

U. S. Patent 7,619,901 (filing date June 25, 2007; patent issued Nov. 17, 2009)